The operation of modern electronic systems is synchronized by a periodic signal known as a clock signal that is provided by a clock generator to control the sequence and pacing of the devices of the electronic circuit. Programmable clock generators intended for high performance consumer, networking, industrial, computing and data communications applications are known in the art. Programmable clock generators may be programmed to generate a plurality of output clock signals from a single reference clock input.
The clock signals generated by the clock generator are provided to other devices within the system. The difference in the length of the conductive traces connecting the clock generator to the other devices results in the clock signal arriving at the various devices at different times. Undesirable clock skew results when the clock signal generated by the clock generator arrives at these devices at different times.
In order to accommodate for the difference in trace lengths, board designers utilizing clock generator chips are commonly required to add physical length to the shorter traces in their board designs to match the longest clock delay in the system or to add delay to the outputs of the clock generator driving shorter length traces. Requiring the board designer to make board level adjustments to accommodate for the clock skew of a clock generator unnecessarily complicates the use of a particular clock generator in a board level design.
Accordingly, what is needed in the art is a system and method for automatically detecting the trace lengths at each output of a clock generator and for adding an appropriate delay to each of the outputs to deskew the clock generator outputs.